The present invention relates to a semiconductor integrated circuit device having a dynamic RAM (DRAM) cell and, more particularly, to an operation scheme of a memory cell array on which crosspoint-type memory cells are integrated and laid out.
Of MOS semiconductor memory devices, a DRAM has the highest integration density because of relatively simple memory cells constituting the DRAM. This trend toward high integration is due partly to increasing miniaturization and three-dimensionally laying out memory cells. However, the development of an optical micropattern exposure technique and complicated process integration technique involving with the three-dimensional layout of memory cells almost reaches its limit. A new breakthrough is required to realize a very high integration density of 4-Gbits or more.
This problem will be described in detail.
FIG. 13A is a block diagram showing the basic arrangement of a folded bit-line scheme. Particularly, FIG. 13A schematically shows the layout of memory cells. FIG. 13B is an enlarged view showing the portion within the broken line 13B in FIG. 13A.
As shown in FIG. 13A, in the folded bit-line scheme, memory cells M are not arranged at all the intersecting points of word lines WL (WL1 to WL4) and bit lines BL (BL1 and /BL; "/" means an inverted signal or negative logic signal) but at half of all the intersecting points. The bit line BL1 and the bit line /BL1 paired with the bit line BL1 are folded on the memory cell array and connected to one sense amplifier SA.
The folded bit-line scheme is excellent in noise immunity. Due to this advantage, the folded bit-line scheme is the main current of the memory cell layout scheme ranging from 64-kbit DRAMs to 64-Mbit DRAMs which are being massproduced.
As shown in FIG. 13B, however, since the memory cells M are arranged at half of all the intersecting points in the folded bit-line scheme, a "MEMORY CELL AREA" within which the memory cells M are laid out must be at least "length necessary for two word lines WL".times."length necessary for one bit line BL".
Letting "F" be the minimum feature size, the folded bit-line scheme can reduce the area to a limit area "4F.times.2F=8F.sup.2 ". For future high integration, memory cells capable of realizing an area of "8F.sup.2 " or less per cell are required as a new breakthrough for satisfying this requirement. One of new breakthroughs is an open bit-line scheme generally employed up to 64-kbit DRAMs.
FIG. 14A is a block diagram showing the basic arrangement of the open bit-line scheme. Particularly, FIG. 14A schematically shows the layout of memory cells. FIG. 14B is an enlarged view showing the portion within the broken line 14B in FIG. 14A.
As shown in FIG. 14A, in the open bit-line scheme, memory cells M are arranged at all the intersecting points of word lines WL (WL1 to WL8) and bit lines BL (BL1, /BL1, BL2, and /BL2). A pair of bit lines BL and /BL connected to one sense amplifier SA (SA1 or SA2) are arranged right and left using the sense amplifier SA as the center.
This open bit-line scheme has demerits that the noise immunity is inferior to the folded bit-line scheme and that the sense amplifier SA must be laid out within the layout pitch of the bit line BL, resulting in a strict design rule.
As shown in FIG. 14B, however, the "MEMORY CELL AREA" within which the memory cells M are laid out suffices to be "length necessary for one word line WL".times."length necessary for one bit line BL". Therefore, the layout of the memory cells M in the open bit-line scheme can greatly reduce the area per memory cell M.
More specifically, letting "F" be the minimum feature size, the open bit-line scheme can reduce the area up to "2F.times.2F=4F.sup.2 ". For the same integration density, the open bit-line scheme can theoretically reduce the area of the memory cell array to 1/2 that of the folded bit-line scheme. This will be a significant breakthrough for high integration.
A memory cell used in the open bit-line scheme is particularly called a crosspoint-type memory cell. An example of a crosspoint-type memory cell realizing area "2F.times.2F=4F.sup.2 ", is an SGT (Surrounding Gate Transistor) cell shown in FIGS. 15A and 15B. The SGT cell is disclosed in reference:
K. Sunouchi et al., "A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMs", IEDM 89-23.
To put a crosspoint-type memory cell realizing the area "4F.sup.2 ", into a practical use based on this background, an important key point is to arrange memory cells not by the open bit-line scheme but by substantially the folded bit-line scheme excellent in noise immunity.
An example which satisfies this key point is a divided/shared bit-line (DSB) sensing scheme proposed by H. Hidaka et al. This is disclosed in reference:
"A Divided/Shared Bit-Line Sensing Scheme for ULSI DRAM Cores", IEEE Journal Solid-state Circuits, Vol. 26, No. 4, pp. 473-478, April 1991.
Even when crosspoint-type memory cells are adopted, the DSB sensing scheme can operate similarly to the sensing scheme of the folded bit-line scheme and is excellent in noise immunity.
The DSB sensing scheme however requires a "restore cycle" which is unnecessary in the folded bit-line scheme.
Further, in the DSB sensing scheme, two transfer gates must operate with clocks before and after a restore.
Under these circumstances, the DSB sensing scheme requires an extra time for ensuring the clock timing margin and is not suitable for realizing a high-speed cycle time.
In addition, three charge/discharge operations for a pair of bit lines are performed during one cycle in the worst case. This increases the number of bit line charge/discharge operations to increase the power consumption.